Lorentz Solution and NVIDIA are positioning advanced electromagnetic (EM) verification as a necessity for the next generation of AI infrastructure. By jointly presenting at the TSMC 2026 Open Innovation Platform (OIP) Ecosystem Forum, the companies aim to demonstrate how automated chip-level 3D EM extraction can address the physical limitations of ultra-high-speed silicon photonics and 3DIC designs. This collaboration highlights a shift toward full-physics sign-off to ensure first-silicon success in distributed compute fabrics.
Automated EM Extraction for Silicon Photonics
The companies will present research on "Large-scale Chip-level 3D EM Extraction and Sign-off of Ultra-high-speed Silicon Photonics and Custom Silicon IC/3DIC Designs with PeakView®." This presentation focuses on the PeakView® xLEM™ technology, which Lorentz claims extends traditional parasitic extraction into a fully automated, chip-level 3D fullwave EM extraction and back-annotation flow. Unlike conventional RC-based parasitic verification, which the company suggests fails to capture critical inductive effects and EM isolation at multi-terabit data rates, xLEM™ works directly from the LVS database. This approach is intended to preserve connectivity across design hierarchies without requiring schematic or layout rework, automatically back-annotating up to thousands of ports with S-parameter and parasitic inductance models reaching terahertz frequencies.
Addressing Distributed Compute Fabric Challenges
As AI data centers evolve into large-scale distributed compute fabrics, millions of accelerators are increasingly connected via ultra-high-bandwidth optical and co-packaged interconnects. At these extreme speeds, interconnects function as distributed electromagnetic structures rather than simple wires. Lorentz is positioning its PeakView® platform as a solution to the signal propagation and loss issues inherent in these advanced IC and 3DIC nodes. By providing LVS-clean electromagnetic verification, the technology seeks to bridge the gap between design and physical reality. The presentation at the TSMC OIP Forum in Santa Clara on September 23, 2026, marks the third consecutive year Lorentz and NVIDIA have showcased EM technologies for real silicon designs to the TSMC ecosystem.
Key Takeaways
- Lorentz and NVIDIA will present joint research on chip-level 3D EM extraction at the TSMC 2026 OIP Forum.
- PeakView® xLEM™ technology provides automated back-annotation of up to thousands of ports with S-parameter and parasitic inductance models up to terahertz.
- The technology is designed to address the failure of conventional RC-based parasitic verification in ultra-high-speed, multi-terabit interconnects.
TechInsyte's Take
In our view, this collaboration signals that the industry is hitting a physical wall where traditional electrical modeling is no longer sufficient for AI scaling. As interconnects move toward terahertz frequencies and silicon photonics become standard, the margin for error in electromagnetic isolation and signal loss vanishes. By moving sign-off from simple parasitic estimation to full-physics 3D EM extraction, Lorentz and NVIDIA are attempting to standardize a more rigorous verification requirement for the entire AI hardware supply chain.
Questions & Answers
How does xLEM™ technology differ from traditional parasitic verification methods?
Traditional RC-based verification often fails to capture critical inductive effects, EM isolation, and lossy signal propagation at multi-terabit speeds. xLEM™ utilizes a fully automated, chip-level 3D fullwave EM extraction flow that works directly from the LVS database to provide more accurate physical modeling.
What specific hardware architectures benefit from this EM sign-off capability?
The technology is specifically targeted at ultra-high-speed AI systems, silicon photonics, and advanced IC/3DIC designs where interconnects behave as distributed electromagnetic structures within large-scale distributed compute fabrics.
What are the operational advantages of using the PeakView® platform for design sign-off?
The platform aims to provide an automated flow that requires no schematic or layout rework and preserves connectivity across any design hierarchy, allowing for the back-annotation of thousands of ports without missing pieces or double counting.
When and where will the technical details of this collaboration be presented?
The joint presentation will take place on September 23, 2026, at the TSMC 2026 Open Innovation Platform (OIP) Ecosystem Forum in Santa Clara, CA.
Source: Businesswire
