Montage Technology has announced the industry's first trial production of its CXL 3.2 Memory eXpander Controller (MXC) chip. Designed for AI, cloud computing, and data center environments, the chip addresses increasing demands for memory expansion and resource pooling. By leveraging CXL technology, the MXC allows infrastructure leaders to build memory systems with higher capacity and improved resource utilization. This development signals a shift toward more flexible memory architectures, providing a technical path to bypass the capacity limits inherent in traditional server hardware.
CXL 3.2 MXC Technical Specifications and Integration
The CXL 3.2 MXC complies with CXL Type 3 specifications, supporting both CXL.mem and CXL.io protocols. It is engineered with PCIe 6.x and CXL 3.2 protocol support, which enables data transfer rates reaching 64 GT/s. To manage backend memory, the chip integrates dual DDR5 memory controllers supporting up to 8000 MT/s. It functions by converting host-side CXL memory requests into DDR commands in real time, facilitating efficient data exchange.
Beyond the controllers, the chip incorporates PCIe 6.x PHY, DDR5 PHY, and dual RISC-V processor subsystems. To ensure deployment flexibility, the MXC supports multiple form factors, including EDSFF modules and PCIe AIC cards. These specifications are intended to support tiered memory architectures, pooling, and general memory expansion. To assist with commercialization, Montage Technology provides a software development kit (SDK) alongside specific analysis and testing tools. These resources are designed to help customers manage compatibility validation and accelerate the transition to mass production for next-generation memory products.
Ecosystem Validation with Samsung, SK hynix, Intel, and AMD
The CXL 3.2 MXC has already undergone initial validation and integration into next-generation products by leading memory module manufacturers Samsung and SK hynix. Samsung's Jangseok Choi noted that the combination of the MXC with DDR5 technology balances performance and capacity for data center customers. Similarly, SK hynix's Uksong Kang highlighted the chip's potential for supporting resource sharing and high-capacity expansion, which are critical factors for generative AI and large language models.
Interoperability is a core focus of the rollout, with the solution designed to align with major server platforms. Dr. Debendra Das Sharma of Intel stated that the MXC demonstrates how the maturing CXL ecosystem can unlock memory expansion capabilities specifically for next-generation Intel Xeon platforms. AMD's Amit Goel also confirmed continued collaboration with Montage Technology to provide a foundation for more efficient and flexible memory architectures. This cross-industry alignment suggests the MXC is positioned to function across the primary compute ecosystems used in modern enterprise data centers, ensuring that the hardware remains compatible with the most widely deployed CPU architectures.
Key Takeaways
- The CXL 3.2 MXC chip supports PCIe 6.x and CXL 3.2 protocols, delivering data transfer rates up to 64 GT/s.
- The chip integrates dual DDR5 memory controllers that support memory speeds up to 8000 MT/s.
- Initial validation has been completed through integration with memory module manufacturers Samsung and SK hynix.
TechInsyte's Take
In our view, the trial production of the CXL 3.2 MXC chip signals that the CXL ecosystem is moving from theoretical specification to tangible hardware deployment. By securing validation from both the primary CPU vendors (Intel and AMD) and the dominant memory providers (Samsung and SK hynix), Montage Technology has minimized the interoperability risks that typically plague new data center standards. This suggests that memory pooling and expansion will soon become viable architectural choices rather than experimental configurations. For infrastructure leaders, this indicates a shift toward disaggregated memory, which could fundamentally change how server capacity is scaled for AI workloads.
Source: BUSINESSWIRE
