The escalating power demands of massive AI clusters are forcing a fundamental redesign of datacenter optical interconnects. fJscaler, Inc. is addressing this constraint by beginning sampling of its 100 GHz BiCMOS transimpedance amplifier (TIA) for intensity-modulation direct-detection (IM-DD) applications. By targeting energy efficiency and high bandwidth, the company aims to support the 1.6T and 3.2T generations of optical interconnects. This development comes as AI infrastructure scaling becomes increasingly limited by the power consumed by optical links, making picojoule-per-bit efficiency a primary metric for datacenter operators and system designers.
Scaling AI Clusters via BiCMOS TIA Sampling
As AI accelerators scale toward hundreds of thousands of units, the power consumption of optical interconnects has emerged as a first-order design constraint. fJscaler is positioning its new BiCMOS TIA to mitigate this by achieving a power efficiency of 0.85 pJ/bit. The device features a bandwidth of 100 GHz and an input-referred noise density of 18 pA/√Hz. These specifications are intended to enable 200G-per-lane and higher serial links, providing the necessary sensitivity headroom for unretimed and linear-drive architectures. The company is currently sampling the TIA to strategic customers, with a next-generation version in development that targets silicon photonics receivers. By utilizing a BiCMOS platform, fJscaler intends to combine SiGe speed with CMOS integration density. This approach aims to preserve signal integrity at high speeds while meeting the dynamic range and linearity requirements demanded by linear pluggable optics and co-packaged architectures in modern datacenter environments.
Expanding Photonic IC Capabilities for 1.6T Applications
Beyond analog electronics, fJscaler is introducing a new family of Photonic IC (PIC) products designed for 1.6T coherent-lite and IM-DD applications. This expansion allows the company to offer a co-optimized toolkit of both electronic and photonic components. The coherent-lite PICs are intended for campus and inter-datacenter reaches, providing a balance of performance and cost compared to full coherent technology. Meanwhile, the IM-DD PICs focus on increasing density and efficiency within the datacenter. The company is optimizing the TIA for operation with back-illuminated InP photodiodes to minimize parasitics at the optical-electrical interface. This integrated strategy is designed to support a wide range of datacenter interconnect needs, from intra-datacenter links to longer-reach applications. By aligning its electronic IC portfolio with these new photonic products, fJscaler is attempting to provide the complete optical engine required for the next wave of high-bandwidth, energy-efficient datacenter infrastructure deployments.
Key Takeaways
- fJscaler has begun sampling a 100 GHz BiCMOS TIA with 0.85 pJ/bit power efficiency.
- The TIA is designed to support 200G-per-lane serial links and 1.6T/3.2T optical interconnect generations.
- A new Photonic IC product family has been unveiled for 1.6T coherent-lite and IM-DD applications.
TechInsyte's Take
In our view, fJscaler’s move to sample a TIA at sub-one picojoule efficiency is a direct response to the "power wall" facing AI infrastructure. As compute density increases, the energy cost of moving data between accelerators becomes as critical as the compute itself. By targeting 0.85 pJ/bit, fJscaler is betting that the industry will prioritize energy-efficient, linear-drive architectures over traditional, high-power alternatives. Furthermore, their dual-track approach—combining BiCMOS electronics with a new Photonic IC family—suggests a strategic shift toward providing fully integrated optical engines. This vertical integration could be vital for customers seeking to minimize parasitics and maximize bandwidth in 1.6T and 3.2T environments.
Questions & Answers
How does the new TIA address the power constraints of AI clusters?
The TIA achieves a power efficiency of 0.85 pJ/bit, which is intended to reduce the energy overhead of optical links. This allows for more compute per watt by minimizing the power consumed during data transmission between accelerators.
What specific technical specifications define the new BiCMOS TIA?
The device delivers a 100 GHz bandwidth, an input-referred noise density of 18 pA/√Hz, and is optimized for use with back-illuminated InP photodiodes to minimize parasitics.
What is the strategic purpose of the new Photonic IC (PIC) product family?
The PIC family targets 1.6T coherent-lite and IM-DD applications, allowing fJscaler to provide a co-optimized toolkit of both photonic and electronic components for various datacenter reaches and cost points.
Which future technologies is fJscaler targeting with its development roadmap?
The company is developing a next-generation TIA version for silicon photonics receivers and is positioning its current technology to support 1.6T and 3.2T generations of optical interconnects.
Source: fJscaler
