Cadence (Nasdaq: CDNS) announced an expanded, multi‑year collaboration with Intel Foundry to accelerate design‑technology co‑optimization (DTCO) for Intel’s upcoming 14A process node. The partnership pairs Cadence’s agentic AI‑driven EDA and IP solutions with Intel’s process and packaging expertise, aiming to speed time‑to‑market for high‑performance computing (HPC) and mobile designs.
Cadence and Intel Foundry Detail the New DTCO Partnership
The agreement adds DTCO work that targets Intel’s next‑generation process technologies, starting with Intel 14A. Cadence will provide AI‑enhanced flows and core products, while Intel will contribute its process innovation and advanced design know‑how. Together they will optimize tools, flows, and methodologies to achieve industry‑leading performance, power, and area (PPA) metrics and to deliver production‑ready process design kits (PDKs). Both companies said the deeper partnership “will leverage the strengths of both companies to empower customers to unlock new levels of performance, power, and efficiency” (Cadence CEO Anirudh Devgan) and “enable deeper co‑optimization… showcasing the ability of both companies to drive innovation at scale” (Intel Foundry EVP Naga Chandrasekaran).
Alignment With Customer Roadmaps and Technology Roadmaps
The collaboration aligns with Intel’s roadmap to provide a robust ecosystem for its 14A node, which is positioned for HPC and mobile workloads. By integrating Cadence’s AI‑driven design tools early in the node’s development, customers can evaluate PPA trade‑offs sooner and reduce design risk. The partnership also expands to cover IP readiness and design enablement, suggesting that Intel’s customers will have access to vetted IP blocks and reference flows that are already tuned for the 14A process.
Implications for Enterprise Design Teams
For enterprise design teams, the joint effort promises earlier access to validated PDKs and AI‑assisted design methodologies, potentially shortening the prototype phase for next‑generation silicon. Cadence’s agentic AI flows are intended to automate portions of the design cycle, which could lower the engineering effort required to meet the stringent PPA targets of the 14A node. The multi‑year nature of the agreement indicates a sustained commitment to co‑optimizing future Intel process generations beyond 14A.
Key Takeaways
- Cadence and Intel Foundry entered a multi‑year DTCO collaboration focused on Intel’s 14A process.
- The partnership combines Cadence’s agentic AI‑driven EDA/IP solutions with Intel’s process and packaging expertise to deliver production‑ready PDKs.
- Both companies highlighted the aim to improve performance, power, and area (PPA) while reducing design risk for HPC and mobile designs.
TechInsyte's Take
The expanded DTCO effort gives enterprise silicon teams a clearer path to adopt Intel’s 14A node with AI‑enhanced tools, but the actual impact on design schedules will depend on how quickly production‑ready PDKs become available. Buyers should monitor the rollout of the AI flows and any early silicon results to gauge whether the promised risk reduction materializes.
Source: Businesswire
