THine Electronics is attempting to bypass the latency and power bottlenecks currently hindering massive AI server scaling by removing Digital Signal Processors (DSPs) from the optical link. The Tokyo-based semiconductor firm announced two new optical products utilizing proprietary ZERO EYE SKEW® technology to facilitate ultra-high-speed data transmission. These solutions aim to support the increasing compute demands between GPUs and memory in next-generation, large-scale AI datacenters.
THine ZERO EYE SKEW® Optical Solutions
The company is introducing two specific optical semiconductor products: the THLD6481, a 64Gbps VCSEL (Vertical-Cavity Surface-Emitting Laser) driver, and the THTA6482, a 64Gbps TIA (Transimpedance Amplifier). These components are engineered to support the PCIe6 standard. By utilizing proprietary circuit technology to eliminate the need for DSPs, THine claims these products can maintain signal integrity while providing higher density and lower costs. The development of these technologies has received partial support through a grant program administered by Japan's National Institute of Information and Communications Technology (NICT). THine intends to showcase these PCIe6 chipsets at the European Conference on Optical Communications (ECOC) 2026 in Málaga, Spain.
Roadmap for PCIe7 and AI Scale-Up
THine is positioning its technology to address the "Scale-Up" requirements of AI servers, which the company suggests may eventually require over 500 xPUs. A critical part of this strategy involves a roadmap for PCIe7 (128Gbps/lane) support, specifically targeting Near-Package Optics (NPO) and Co-Packaged Optics (CPO). The company plans to provide samples of these DSP-free Electronic Integrated Circuits (EICs) for PCIe7 in 2027. According to THine, these future PCIe7 solutions could reduce latency by 90% and decrease power consumption by 73% when compared to traditional DSP-based optical interconnects. Additionally, the company has initiated product planning for driver and TIA solutions targeting UCIe retimers.
Key Takeaways
- THine introduced the THLD6481 64Gbps-VCSEL driver and THTA6482 64Gbps-TIA to support PCIe6.
- The company expects to provide PCIe7 (128Gbps/lane) DSP-free EIC samples in 2027.
- THine claims its PCIe7 technology can reduce latency by 90% and power consumption by 73% versus DSP-based interconnects.
TechInsyte's Take
In our view, THine is betting that the massive power and latency penalties of DSP-based optical interconnects will become the primary ceiling for AI datacenter growth. By stripping the DSP out of the equation via ZERO EYE SKEW® technology, they are targeting the most expensive and heat-intensive part of the high-speed data path. If their 2027 PCIe7 roadmap delivers the promised 90% latency reduction, it could fundamentally change how architects approach GPU-to-memory scaling and co-packaged optics in hyperscale environments.
Questions & Answers
How does THine's technology address the power constraints of AI datacenters?
The company aims to eliminate Digital Signal Processors (DSPs) from the optical link. By removing these components, THine claims its PCIe7 solutions can reduce power consumption by 73% compared to current DSP-based optical interconnects.
What specific industry standards are these new products designed to support?
The current 64Gbps products (THLD6481 and THTA6482) are designed for PCIe6. The company's future roadmap targets PCIe7 at 128Gbps per lane, as well as UCIe retimers.
What is the strategic significance of the "Scale-Up" AI server mention?
THine suggests that as AI use cases expand, servers may require over 500 xPUs. This level of density requires ultra-low latency and high-speed data transmission between GPUs and memory, which THine is attempting to enable through its DSP-free optical chipsets.
When can enterprises expect to see these advanced PCIe7 components?
THine is planning to release samples of its DSP-free EICs for PCIe7 in 2027.
Source: Businesswire
