The push toward 1.6T AI connectivity is forcing a fundamental shift from static hardware configurations to intelligent, adaptive electrical interfaces. TeraSignal and Keysight Technologies are positioning themselves at the center of this transition by announcing a live demonstration of CMIS Link Training (CMIS-LT) at ECOC 2026 in Málaga, Spain. This collaboration aims to showcase how 200G/lane high-speed links can utilize standardized frameworks to coordinate settings between interoperable devices, addressing the mounting signal integrity challenges inherent in scaling AI infrastructure.
TeraSignal and Keysight CMIS-LT Demonstration
The upcoming demonstration, scheduled for September 21-23 at the OIF booth #2126, focuses on the operational mechanics of CMIS-LT within a 200G/lane high-speed link environment. TeraSignal intends to utilize its TSLink™ technology alongside its Analog Wave Processor (AWP) architecture to illustrate how devices can coordinate link parameters and adapt to real-time channel conditions. To validate these high-speed operations, Keysight will provide advanced test and measurement support, specifically deploying its M8050A 120 GBaud High-Performance Bit Error Ratio Tester (BERT) and its N1060A 85 GHz Precision Waveform Analyzer. This technical showcase is part of a broader OIF interoperability demonstration involving 39 companies, which seeks to validate various interfaces including 448G & 224G Common Electrical I/O (CEI) and Co-Packaging. By demonstrating these capabilities in a multi-vendor setting, the companies are testing whether standardized link training can effectively manage the complexities of next-generation AI cluster architectures and the resulting electrical interface requirements.
Addressing 200G/lane Signal Integrity Challenges
As AI infrastructure scales toward 200G/lane signaling, the margin for error in signal integrity narrows significantly due to increased channel loss, reflections, and component variation. TeraSignal CEO Armond Hairapetian suggests that 200G/lane connectivity requires links to move away from static configurations that attempt to accommodate every possible channel scenario. Instead, the company is proposing a model where the link "understands" its environment to optimize itself via CMIS Link Training. This approach aims to mitigate the performance fluctuations caused by differences in system implementation across interoperable devices. Keysight’s Dr. Joachim Peerlings notes that as AI cluster architectures grow in complexity, ecosystem-wide interoperability becomes a critical requirement for customers. The demonstration serves as a technical proof point for how open, standards-based technologies can facilitate the deployment of 1.6T AI interconnect solutions. By utilizing adaptive linear interconnects, the goal is to provide a framework where interoperating devices can maintain stable, optimized connections despite the physical limitations and environmental variables present in high-speed data center environments.
Key Takeaways
- TeraSignal and Keysight will demonstrate CMIS Link Training on a 200G/lane high-speed link at ECOC 2026 in Málaga, Spain.
- The demonstration utilizes TeraSignal’s TSLink™ technology and Analog Wave Processor (AWP) architecture to enable adaptive link optimization.
- Keysight will support the live demo using the M8050A 120 GBaud BERT and the N1060A 85 GHz Precision Waveform Analyzer.
TechInsyte's Take
In our view, this collaboration highlights a critical pivot in data center architecture: the transition from "dumb" copper and optical paths to "intelligent" adaptive interconnects. As AI workloads drive the industry toward 1.6T speeds, the physical layer can no longer rely on over-provisioned, static settings to guarantee stability. This demonstration signals that the industry is looking toward standardized, software-driven coordination—specifically through CMIS-LT—to manage the extreme sensitivities of 200G/lane signaling. If successful, this move toward intelligent linear connectivity could reduce the reliance on costly, high-margin hardware compensations by allowing the interface to dynamically adjust to the specific electrical realities of the channel.
Questions & Answers
How does CMIS Link Training address the scaling challenges of 1.6T AI connectivity?
CMIS Link Training provides a standardized framework that allows interoperating devices to coordinate electrical interface settings and adapt to changing channel conditions, such as channel loss and reflections, which become more problematic at 200G/lane speeds.
What specific hardware is being used to validate the 200G/lane link performance?
Keysight is deploying its M8050A 120 GBaud High-Performance Bit Error Ratio Tester (BERT) and its N1060A 85 GHz Precision Waveform Analyzer to support the live demonstration.
What is the strategic role of TeraSignal's TSLink™ technology in this demonstration?
TSLink™ is designed to use CMIS Link Training to coordinate link parameters between devices, enabling the link to adapt its operation to actual channel conditions rather than relying on a fixed, static configuration.
Where and when will the interoperability demonstration take place?
The demonstration will occur at the OIF booth #2126 during the ECOC 2026 event in Málaga, Spain, from September 21 to September 23.
Source: Businesswire
