Marvell is positioning its next-generation hardware to solve the critical memory constraints currently throttling large-scale AI inference and machine learning workloads. By launching the second-generation Structera X 3406 and 3506 CXL 3.2 memory expanders, the company aims to provide hyperscale and enterprise providers with a scalable method to bypass the physical limitations of traditional server architectures. These new controllers are designed to address the massive memory demands driven by expanding Large Language Model (LLM) sizes, growing context windows, and increasing KV-cache requirements. As AI models grow in complexity, the ability to expand memory capacity without sacrificing performance becomes a primary requirement for maintaining high throughput and XPU utilization. Marvell is betting that its specialized CXL (Compute Express Link) architecture will allow data center operators to build more efficient, disaggregated memory pools that can scale alongside compute power.
Scaling Capacity via Six-Channel CXL 3.2 Architecture
The second-generation Structera X series introduces a significant jump in hardware density and connectivity compared to its predecessors. The 3406 and 3506 controllers feature an industry-first six-channel design, representing a 50% increase in memory channels over the previous generation. This architectural shift allows the Structera X 3406 to support up to 9TB of DDR4 via 18 RDIMM slots, while the Structera X 3506 supports up to 6TB of DDR5 via 12 RDIMM slots. To maintain high-speed data movement, Marvell has integrated PCIe Gen 6 connectivity, providing up to 256GB/s of host bandwidth through PCIe 6.0 x16.
Beyond simple capacity expansion, Marvell is targeting memory utilization efficiency through multi-host sharing and advanced compression. The controllers enable memory capacity sharing across up to four hosts, a move intended to reduce "stranded memory" within AI clusters. Furthermore, the company has implemented inline LZ4 compression, which boasts a throughput of up to 250GB/s—a fivefold increase over the previous generation. Marvell claims this compression can deliver up to 2–3x more effective memory capacity depending on the specific workload. For Deep Learning Recommendation Models (DLRM), the company expects these features to yield up to 2x higher queries per second and 2–3x more effective embedding-table capacity per controller. For LLM serving, the hardware is designed to provide up to 40–50% faster time to first token (TTFT) at equivalent context lengths, or potentially double the supportable context window at equivalent latency.
Addressing AI Inference and Data Security Requirements
As AI workloads shift toward more agentic and complex behaviors, the technical requirements for memory reliability and security are intensifying. Marvell is addressing these needs through its StructGuard enterprise-grade RAS (Reliability, Availability, and Serviceability), which provides advanced error correction to mitigate risks from DRAM device failures. Additionally, the company is incorporating post-quantum security measures, combining post-quantum cryptography, Caliptra 2.0, CXL IDE, and AES-256 memory encryption to protect sensitive data within the expanded memory pool.
The deployment of these controllers is supported by a broad ecosystem of industry partners. Marvell is collaborating with major memory vendors, including Samsung Electronics and SK hynix, to ensure compatibility and reliability. The company is also working with platform providers like AMD and Arm to integrate these CXL solutions into existing processor ecosystems. Furthermore, Marvell has noted active collaborations with hyperscalers, such as Alibaba, to develop memory architectures specifically for large-scale AI and cloud infrastructure. While the Structera X 2404 and 2504 architectures are already shipping to hyperscalers, the new 3406 and 3506 models are currently being demonstrated at the OCP Summit and are expected to enter the sampling phase in Q1 2027. This timeline suggests a long-term strategic play to capture the infrastructure layer of the next era of AI-driven computing.
Key Takeaways
- The Structera X 3406 and 3506 controllers feature six DDR4/DDR5 channels, a 50% increase over the previous generation, supporting up to 9TB of DDR4 or 6TB of DDR5.
- Marvell's inline LZ4 compression provides up to 250GB/s of throughput, which the company claims can deliver 2–3x more effective memory capacity.
- The new controllers are expected to begin sampling in Q1 2027 and feature PCIe Gen 6 connectivity with support for up to four hosts.
TechInsyte's Take
In our view, Marvell’s move into high-channel-count CXL expansion is a direct response to the "memory wall" that currently limits the ROI of high-end AI accelerators. As LLMs demand larger KV-caches and wider context windows, the bottleneck is no longer just raw compute, but the ability to feed that compute with massive, low-latency memory volumes. By integrating LZ4 compression and multi-host sharing, Marvell is not just selling more capacity; they are selling higher utilization rates.
This signals a broader industry shift toward disaggregated memory architectures. Instead of being locked into the physical DIMM slots of a single CPU, enterprises will increasingly look to CXL to create flexible, shared memory pools. If Marvell can successfully deliver on the promised 40–50% improvement in time to first token, they will become a critical component in the AI inference stack. However, the Q1 2027 sampling date indicates that this is a long-term play, leaving a window for competitors to address the immediate, pressing memory shortages facing data center operators today.
Questions & Answers
How does the new Structera X architecture improve AI inference performance?
The architecture addresses memory-bound workloads, such as LLM serving and DLRM, by increasing memory bandwidth and capacity. Specifically, it aims to deliver up to 40–50% faster time to first token (TTFT) for LLMs and up to 2x higher queries per second for DLRM workloads through increased channels and inline LZ4 compression.
What are the specific capacity limits for the new 3406 and 3506 controllers?
The Structera X 3406 supports up to 9TB of DDR4 memory using 18 RDIMM slots. The Structera X 3506 supports up to 6TB of DDR5 memory using 12 RDIMM slots.
How does Marvell address data security and reliability in these memory expanders?
Marvell utilizes StructGuard enterprise-grade RAS for advanced error correction to enhance reliability against DRAM failures. For security, the controllers incorporate post-quantum cryptography, Caliptra 2.0, CXL IDE, and AES-256 memory encryption.
When will these new CXL 3.2 memory expanders be available for enterprise use?
The Marvell Structera X 3406 and 3506 controllers are expected to enter the sampling phase in Q1 2027.
Source: Marvell
