IQM Quantum Computers announced a new family of quantum error‑correcting codes—directional tile codes—that lower logical error rates by up to 1,000 times compared with the widely used surface code. The result, detailed in an arXiv pre‑print co‑authored with researchers from Freie Universität Berlin, the University of Edinburgh and Johannes Gutenberg‑Universität Mainz, demonstrates the improvement using only the native nearest‑neighbour iSWAP gates of IQM’s Crystal processors. The breakthrough aligns with IQM’s roadmap toward fault‑tolerant quantum computing by 2030 and its upcoming Nasdaq listing via a merger with Real Asset Acquisition Corp.
Directional Tile Codes Deliver Near‑Term Error‑Rate Reduction
The study shows that directional tile codes can achieve a per‑logical‑per‑round error‑rate reduction of up to 1,000× relative to the surface code, while requiring a comparable hardware footprint of roughly 30 physical qubits per logical qubit. Crucially, the implementation relies solely on the nearest‑neighbour connectivity already present in IQM’s Crystal architecture, avoiding any need for new hardware components. Dr. Inés de Vega, IQM’s Chief Scientist, emphasized that the codes “deliver up to a 1,000‑fold reduction in logical error rates on near‑term‑sized IQM Crystal hardware while relying only on practical nearest‑neighbour connectivity.” The research highlights dynamic syndrome extraction circuits that enable the codes to run on a square qubit grid, a design choice that matches IQM’s planar hardware.
Co‑Design of Codes and Hardware Underpins IQM’s Roadmap
IQM positions the directional tile codes as a concrete step toward its 2030 fault‑tolerant target, which envisions scaling quantum processors to one million qubits. The company’s strategy stresses tight co‑design between error‑correction algorithms and manufacturable hardware. Dr. Vincent Steffan, Senior Quantum Error‑Correction Engineer at IQM, noted that the team has been developing tile codes since 2025 because of their “local checks, great parameters, and the many ways that exist to perform logical computation with them without adding connectivity requirements.” By demonstrating the codes on the existing Crystal processors, IQM establishes a baseline for future improvements that can arise from continued co‑design efforts.
Relevance for Enterprise Quantum Buyers
IQM has sold 23 quantum systems worldwide, serving research institutions, high‑performance computing centres and enterprises. The new error‑correction capability could make IQM’s current hardware more attractive to organizations seeking to run deeper quantum circuits without waiting for next‑generation devices. Since the codes do not require hardware changes, existing IQM customers may adopt the technique through software updates or firmware upgrades, potentially extending the useful life of their installations. The announced reduction in logical error rates also narrows the gap between today’s noisy intermediate‑scale quantum (NISQ) devices and the fault‑tolerant regime required for commercially relevant workloads.
Key Takeaways
- Directional tile codes reduce per‑logical‑per‑round error rates by up to 1,000 × versus the surface code, using only the nearest‑neighbour iSWAP gates native to IQM’s Crystal processors.
- The implementation needs roughly 30 physical qubits per logical qubit, matching the hardware footprint of existing surface‑code approaches.
- IQM has sold 23 quantum systems globally, and the new codes can be applied to its current hardware without additional physical modifications.
TechInsyte's Take
The announcement shows that significant error‑correction gains are possible on existing superconducting platforms, reinforcing IQM’s co‑design philosophy. While the codes promise a dramatic logical error reduction, real‑world performance will depend on integration into customer workflows and the stability of the underlying hardware. Enterprises should monitor IQM’s rollout plans and any forthcoming software updates that enable directional tile codes on deployed systems.
Source: Businesswire
