At the 2026 VLSI Symposium, Intel Foundry provided a comprehensive update on its process roadmap and long-term innovation investments. A primary highlight was the announcement that Intel 18A-P, the first performance enhancement within the Intel 18A family, has entered risk production. According to Naga Chandrasekaran, executive vice president and general manager of Intel Foundry, these updates signal the company's long-term commitment to leading-edge process innovation for its customers and partners.
Intel 18A-P Performance and Design Specifications
Intel 18A-P is designed to be fully design rule compatible with Intel 18A, which enables the straightforward reuse of existing design flows and IP. The process maintains a contacted poly pitch of 50nm and offers two cell heights (180nm and 160nm). By utilizing a mix of transistor, interconnect, and design-technology co-optimizations, Intel 18A-P delivers 9% higher performance at iso-power or 18% lower power at iso-performance compared to the standard Intel 18A.
Technical advancements contributing to these gains include:
- Power Boost: A new dual contact, low resistance transistor option that increases drive current and frequency at matched capacitance.
- Thermal and Resistance Gains: A 20-40% improvement in thermal resistance and a 10-30% improvement in via resistance—the vertical connections between chip layers—through materials and geometric optimizations.
- Design Flexibility: The introduction of a fifth logic Vt pair between ULVT and LVT to help designers balance speed and power, alongside new low-power and high-performance transistor options.
- Mobility: PMOS via strain engineering to increase the efficiency of current movement through the transistor.
Backside Power Delivery and GAA Integration
Intel Foundry detailed the operational advantages of gate-all-around (GAA) transistors and backside power delivery (BSPD), both of which reached the market last year with Intel 18A. Vice President and Fellow Eric Karl reported that BSPD and GAA provide an 11% routed area reduction and a 10X reduction in dynamic voltage droop. These factors enable a frequency uplift of up to 6% or a dynamic power reduction of more than 15% compared to comparable frontside interconnect technology.
Further silicon results from CPU cores built on these processes showed stronger frequency scaling at lower voltages. Specifically, research presented by Manju Shamanna from the Silicon and Platform Engineering group demonstrated a frequency improvement of approximately 30% at low voltage (~0.5V) while reducing IR drop and enabling more efficient operation.
Long-Term R&D and Future Silicon Scaling
Intel presented three primary research directions aimed at scaling logic beyond current capabilities:
- Complementary FET (CFET): Intel demonstrated monolithic CFET inverters with vertically stacked NMOS and PMOS devices at a 45nm gate pitch, positioning this vertical device architecture as a path for logic scaling beyond GAA transistors.
- GaN + Si Integration: The company demonstrated 300mm monolithic integration of gallium nitride power devices with silicon logic. This includes a ~1,000 gate digital control block, which Intel says reduces system complexity by enabling large-scale digital control and high-performance power devices in one process.
- Ruthenium Interconnects: Intel demonstrated subtractive ruthenium with airgap integration. This approach achieved up to ~35% capacitance reduction and measurable frequency gains over copper, suggesting a viable path for resistance capacitance scaling as interconnects shrink.
Key Takeaways
- Intel 18A-P has entered risk production, offering 18% lower power at iso-performance or 9% higher performance at iso-power compared to Intel 18A.
- Backside power delivery and GAA transistors have demonstrated a 10X reduction in dynamic voltage droop and an 11% reduction in routed area.
- Long-term R&D milestones include monolithic CFET inverters at a 45nm gate pitch and subtractive ruthenium interconnects that reduce capacitance by up to 35% versus copper.
TechInsyte's Take
The transition of Intel 18A-P into risk production signals Intel's attempt to maintain a tight roadmap for performance iterations. While the immediate gains in power and thermal resistance are concrete, the long-term viability of CFET and ruthenium interconnects remains in the research phase. Infrastructure leaders should monitor how these specific power-efficiency gains translate to real-world CPU core performance as these processes move toward full production.
Source: Businesswire
