Credo Technology Group Holding Ltd is targeting the critical memory bottlenecks currently stifling AI inference performance by introducing a scalable memory expansion solution for programmable logic. At the 2026 OCP Global Summit in San Jose, the company is demonstrating its OmniConnect Weaver memory fanout gearbox integrated with AMD Versal AI Edge Series Gen 2 adaptive SoC architecture. This development aims to provide system integrators with terabyte-class memory capacity and high bandwidth, capabilities that were previously restricted to custom Application-Specific Integrated Circuits (ASICs), now accessible through more flexible, programmable environments.
OmniConnect Weaver and AMD Versal Integration
The collaboration between Credo and AMD has resulted in a working emulation platform that utilizes OmniConnect Weaver to perform memory disaggregation. By running this technology on the AMD Versal AI Edge Series Gen 2 adaptive SoC, the system enables terabytes-class LPDDR memory access. A significant technical distinction of this architecture is its ability to deliver high capacity and bandwidth to a programmable-logic XPU over Very Short Reach (VSR) links using standard organic packaging, notably without the requirement for a silicon interposer. This approach suggests a method for scaling memory infrastructure while avoiding the complexities and costs often associated with advanced packaging techniques. Furthermore, the expanded memory remains transparent above the controller, meaning existing application software can run unmodified. This transparency is designed to allow enterprises to scale their memory pools and throughput without necessitating fundamental rewrites of their current AI inference software stacks, potentially accelerating the deployment of larger-scale models.
Addressing the AI Inference Memory Wall
As AI inference workloads continue to scale, the industry is encountering a "memory wall" where memory bandwidth and capacity constrain performance more significantly than raw compute throughput. Credo is positioning its OmniConnect Weaver memory gearbox as a direct solution to this bottleneck. By linking this technology with the highly programmable AMD Versal platform, the company intends to offer a faster time-to-market for developers who require high-performance memory architectures but prefer the flexibility of programmable logic over the rigidity of custom silicon. AMD is framing this collaboration as a practical pathway for customers to achieve higher memory performance while maintaining the power efficiency and design flexibility inherent in programmable logic. This integration seeks to bridge the gap between the high-performance requirements of next-generation AI systems and the need for adaptable, cost-effective hardware architectures that can evolve alongside shifting workload demands.
Key Takeaways
- Credo is demonstrating its OmniConnect Weaver memory fanout gearbox on AMD Versal AI Edge Series Gen 2 adaptive SoC evaluation boards.
- The platform enables terabytes-class LPDDR memory capacity and high bandwidth via VSR links using standard organic packaging without a silicon interposer.
- The architecture allows application software to run unmodified because the expanded memory is transparent above the controller.
TechInsyte's Take
In our view, Credo’s move to bring ASIC-level memory capabilities to programmable logic is a strategic attempt to democratize high-performance AI infrastructure. By eliminating the need for expensive silicon interposers and custom ASIC development, they are lowering the barrier to entry for scaling AI inference. This signals a shift where the "memory wall" is being addressed not just through raw compute power, but through sophisticated interconnect and disaggregation strategies. For enterprise IT leaders, this suggests a future where hardware flexibility and massive memory scaling can coexist, potentially reducing the long-term technical debt associated with rigid, custom-silicon deployments in rapidly evolving AI environments.
Questions & Answers
How does this technology impact existing AI software deployments?
The expanded memory is designed to be transparent above the controller, which allows application software to run unmodified. This enables enterprises to scale memory capacity and bandwidth without the need for fundamental software re-engineering.
What specific hardware advantage does the Credo and AMD integration offer regarding packaging?
The platform enables terabytes-class LPDDR memory access using standard organic packaging and VSR links, specifically avoiding the need for a silicon interposer, which is often required for high-performance memory scaling.
Why is memory capacity becoming a primary concern for AI inference?
According to Credo, as AI inference workloads scale, memory bandwidth and capacity have become critical bottlenecks that often constrain system performance more than compute throughput itself.
What is the strategic value of using programmable logic instead of custom ASICs?
Using the AMD Versal adaptive SoC platform provides a highly programmable environment that offers faster time-to-market and greater flexibility compared to custom ASICs, while the Credo integration aims to provide the high-performance memory previously reserved for custom silicon.
Source: Credo
