Marvell Technology has unveiled the Teralynx T100, a groundbreaking 102.4 Tbps switch silicon that is explicitly engineered for the AI era and modern cloud data‑center infrastructure. Built on an advanced 3 nm process, the T100 is the first switch of its class to combine a monolithic 102.4 Tbps data path with a purpose‑built architecture that strips away legacy circuitry, thereby slashing power draw and latency. In an environment where GPU‑ and XPU‑driven racks are rapidly approaching 120 kW per rack, the T100’s sub‑1 kW typical power consumption and industry‑leading latency promise to keep air‑cooling viable, reduce the need for costly liquid‑cooling retrofits, and enable operators to pack more accelerators into existing power envelopes. Marvell will begin sampling the device to customers this quarter, positioning the T100 as a direct replacement for older switching platforms that were designed for traditional enterprise and cloud workloads rather than the power‑intensive, bandwidth‑hungry AI workloads of today.
Marvell Announces the Teralynx T100 Switch
Marvell announced the availability of the Teralynx T100, a 102.4 Tbps switch built on a 3 nm process. The company said the silicon is “purpose‑built for AI—designed without the legacy baggage that inflates power” and will begin sampling to customers this quarter. The T100 is positioned as a replacement for legacy switching platforms that were designed for traditional enterprise and cloud workloads rather than the power‑intensive AI era.
The announcement emphasizes that the T100 is a monolithic device—all 102.4 Tbps of bandwidth are integrated on a single die, eliminating the need for multiple chips and associated interconnects that traditionally add both power overhead and design complexity. By removing these legacy elements, Marvell claims the switch can achieve up to 25 % lower power consumption compared with competing solutions that still rely on older architectures. The company also highlights that the T100 delivers the lowest latency observed at this bandwidth tier, a critical factor for AI training and inference where even microsecond‑level delays can degrade GPU utilization and extend model convergence times.
In addition to the performance metrics, Marvell’s press release notes that the T100 will be made available in three distinct package formats—ball‑grid‑array (BGA), co‑packaged copper (CPC), and co‑packaged optics (CPO)—to give hyperscalers and cloud operators flexibility in how they integrate the silicon into existing chassis, rack designs, and optical modules. This packaging diversity is intended to simplify adoption across a range of deployment scenarios, from dense, air‑cooled racks to liquid‑cooled hyperscale pods.
Power Efficiency and Latency Advantages
The T100 consumes under 1 kW typical power, delivering up to 25 % lower power than competitive solutions. Marvell notes that switching and networking components currently account for roughly 15‑25 % of total rack power, making low‑power silicon a strategic requirement for AI data centers. By reducing power per switch, operators can place more GPUs or XPUs within existing power envelopes, avoiding the need for additional power infrastructure or extensive liquid‑cooling systems. The architecture also provides the industry’s lowest latency at the 102.4 Tbps bandwidth tier, which Marvell says helps improve GPU utilization, lower tail latency, and shorten training convergence times.
The source explains that GPU‑ and XPU‑based systems are approaching 120 kW per rack, pushing traditional air‑cooling to its limits and often forcing data‑center operators to invest in complex liquid‑cooling solutions. Because the T100’s typical power draw is under 1 kW, it can be deployed in these high‑density racks without exceeding the existing power budget, effectively “breaking the AI power wall.” Moreover, the reduction in power translates directly into lower heat output, which in turn eases cooling requirements and can reduce overall data‑center operating expenses (OPEX).
Latency is equally critical. The T100’s low‑latency design stems from its high‑radix, flat‑fabric architecture, which reduces the number of network hops required to move data between accelerators. Fewer hops mean less queuing delay and lower tail latency, both of which are essential for maintaining high GPU utilization during large‑scale training runs. Marvell asserts that this latency advantage improves deterministic performance, enabling faster iteration cycles for AI researchers and more predictable inference response times for production workloads.
Scale‑Out, Scale‑Up, and Deployment Flexibility
The Teralynx T100 supports a 512‑port radix, enabling fewer network tiers and simpler fabrics for scale‑out AI clusters that may contain tens of thousands of accelerators. For scale‑up scenarios, the switch’s programmable pipeline accommodates emerging interconnect standards such as the Ethernet Scale‑Up Networking (ESUN) protocol and Ultra Ethernet Consortium (UEC) requirements. Marvell offers the T100 in multiple package formats—including ball‑grid‑array (BGA), co‑packaged copper (CPC), and co‑packaged optics (CPO)—providing hyperscalers and cloud operators flexibility in form factor and connectivity. The device also includes integrated telemetry, AI‑native congestion control, and proprietary traffic‑management logic, and it is compatible with the Open Compute Project’s Switch Abstraction Interface (SAI) and the SONiC operating system.
The 512‑port radix is the highest available in Marvell’s current portfolio and allows operators to consolidate what would traditionally be multiple layers of switches into a single tier. This consolidation reduces the total number of optical links, cuts cabling complexity, and lowers the overall total cost of ownership (TCO) for large AI clusters. For scale‑out deployments—where the goal is to connect tens of thousands of GPUs across a distributed fabric—the T100’s high radix enables a flatter topology that minimizes latency and maximizes bandwidth per accelerator.
Conversely, in scale‑up environments where a smaller number of racks require extremely high bandwidth per link, the T100’s programmable pipeline can be tuned to support emerging standards such as ESUN and the latest UEC specifications. This flexibility ensures that the switch can evolve alongside the rapidly changing AI Ethernet ecosystem, protecting customers’ investments as new protocols become mainstream.
Marvell also stresses the importance of software openness. The T100 ships with a full SDK, supports the Open Compute Project’s Switch Abstraction Interface (SAI), and is compatible with SONiC, the open‑source network operating system widely adopted by hyperscalers. This software stack enables data‑center operators to integrate the switch into existing orchestration frameworks, automate provisioning, and apply AI‑specific traffic‑management policies without vendor lock‑in.
Finally, the three packaging options address distinct deployment constraints. BGA packages are ideal for traditional board‑level integration, CPC offers a high‑density copper interconnect solution for tight‑space racks, and CPO provides an optical‑centric approach that can extend reach while maintaining low power. By offering all three, Marvell gives customers the ability to choose the optimal form factor for their specific power, cooling, and latency targets.
Key Takeaways
- Marvell’s Teralynx T100 is the first 102.4 Tbps switch silicon purpose‑built for AI, sampling begins this quarter.
- The switch consumes under 1 kW typical power, delivering up to 25 % lower power than competing solutions.
- It supports a 512‑port radix and multiple package options (BGA, CPC, CPO), enabling both scale‑out and scale‑up AI fabric deployments.
TechInsyte's Take
The Teralynx T100 gives AI‑focused data centers a silicon option that directly addresses the power and latency constraints of large GPU racks. While the announced efficiencies are compelling, actual impact will depend on how quickly hyperscalers adopt the new form factors and integrate the switch into existing fabric standards. Buyers should monitor early sampling results and evaluate the compatibility of the T100’s traffic‑management features with their current networking stacks.
Source: Businesswire
