Scaling AI and network infrastructure requires moving beyond simple physical-layer testing to address complex system-level errors. Keysight Technologies has launched the FITS-16CH digital-layer error performance validation system to address this shift toward 1.6T technologies. By doubling the channel density of its previous 8-channel offering, the new system provides 16 transmit and 16 receive channels. This expansion aims to help engineers validate complete interconnect assemblies across research, manufacturing, and large-scale AI deployments, ensuring that digital-layer performance remains stable as data center speeds continue to climb.
Keysight FITS-16CH Digital-Layer Expansion
The FITS-16CH system targets the increasing difficulty of maintaining signal integrity in high-speed environments. As interconnect speeds rise, testing only the physical layer fails to capture the full scope of system-level error performance. To mitigate this, the FITS-16CH combines bit error ratio (BER) and forward error correction (FEC) measurements at the digital layer. This allows for the evaluation of complete assemblies under real-world conditions, supporting 106G and 212G lane-rate validation. The platform is designed to accommodate today’s 800G interconnects and emerging 1.6T technologies. Keysight is positioning this tool to support a wide array of hardware, including full-retimed optics (FRO), active optical cables (AOCs), linear-retimed optics (LRO), linear pluggable optics (LPO), active copper cables (ACCs), active electrical cables (AECs), passive direct attach cables (DACs), and high-speed copper flyover cables used in high-performance computing.
Automated Lane Tuning and Integration Capabilities
To manage the complexity of 1.6T margins, the FITS-16CH utilizes a Windows 11 graphical user interface that integrates with the Keysight DCA-X. This integration enables automated lane tuning, which calculates optimal transmit finite impulse response (FIR) tap settings to open the electrical eye. According to the company, this automation can reduce tuning time from weeks or days of manual effort to just a few minutes. The system supports two Module Compliance Boards (MCBs) with independent channel groups, allowing for simultaneous multi-lane validation. For enterprise workflows, the platform offers flexible integration with Keysight data communications analyzers (DCAs), bit error ratio testers (BERTs), and UXR real-time oscilloscopes. It also includes SCPI API support for automation, alongside automatic real-time charting and report generation in PDF and .csv formats.
Key Takeaways
- The FITS-16CH provides 16 transmit and 16 receive channels, doubling the density of the previous FITS-8CH model.
- The system enables validation for 106G and 212G lane rates, supporting both 800G and 1.6T interconnect technologies.
- Automated FIR tap tuning via the Keysight DCA-X can reduce validation timelines from weeks to minutes.
TechInsyte's Take
In our view, the move toward 1.6T interconnects is fundamentally changing the definition of "reliable" hardware. As Credo Technologies' Ameet Suri noted, the tighter margins at these speeds make isolated link testing insufficient; performance must be evaluated at the system level. Keysight’s expansion into digital-layer validation—specifically combining BER and FEC measurements—signals that the industry is hitting a threshold where physical-layer compliance no longer guarantees operational stability. For data center operators and hardware manufacturers, this shift suggests that investment in automated, high-density validation tools is becoming a prerequisite for managing the error rates inherent in next-generation AI and high-performance computing infrastructure.
Questions & Answers
How does the FITS-16CH improve upon previous validation density?
The FITS-16CH provides 16 transmit and 16 receive channels, which represents twice the channel density of the earlier FITS-8CH system, allowing for more simultaneous lane validation.
What specific technical metrics does the FITS-16CH measure to ensure system stability?
The system combines bit error ratio (BER) and forward error correction (FEC) measurements at the digital layer to evaluate how complete interconnect assemblies perform under real-world conditions.
Which interconnect types are supported by this new validation platform?
The platform supports a broad range of technologies, including FRO, AOCs, LRO, LPO, ACCs, AECs, DACs, and high-speed copper flyover cables.
How does the FITS-16CH address the time constraints of manual hardware tuning?
By integrating with the Keysight DCA-X, the system automates the calculation of optimal transmit finite impulse response (FIR) tap settings, potentially reducing tuning time from weeks to a few minutes.
Source: Keysight
